RTL Design Verification Engineer — PCIe

Job Description

Chiplogic Technologies is hiring an RTL Design Verification Engineer with deep PCIe expertise for its Bengaluru semiconductor team. Salary band: ₹24,55,765 – ₹40,90,091 per year. In this role you will own the verification of PCIe controller / endpoint / root-complex IP — building SystemVerilog / UVM testbenches, integrating PCIe VIPs, defining and tracking coverage, and driving regressions to closure. You will work closely with RTL design, architecture and silicon validation teams to debug failures, characterize corner cases (LTSSM, link training, equalization, ECRC, AER, MSI-X) and contribute to verification methodology improvements across projects. You bring: a Bachelor's or Master's in Electronics / Computer Engineering, 5+ years of pre-silicon functional verification on complex ASIC IPs, strong SystemVerilog and UVM, hands-on experience with PCIe (Gen3/Gen4/Gen5 preferred), commercial VIPs (Cadence / Synopsys), coverage-driven verification and assertion-based methodologies, and Linux-based EDA flows. Nice to have: CXL, DMA engines, low-power verification, formal methods, or scripting in Python / Perl.

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