Sr. Digital Design Engineer — Semiconductor / VLSI

Job Description

Noesis IT is hiring a Senior Digital Design Engineer for an in-person VLSI / Semiconductor role in Bengaluru. Salary band: ₹35,00,000 – ₹50,00,000 per year. What you will do: - Own RTL design for complex digital blocks — write clean, synthesizable Verilog / SystemVerilog and drive blocks from spec to GDSII handoff. - Partner with verification, DFT, synthesis, PnR and silicon teams to close timing, power and area at advanced process nodes. - Run lint, CDC, RDC and formal checks; resolve issues with synthesis, STA and back-end teams. - Contribute to architecture decisions, micro-architecture documentation and design reviews. - Mentor junior engineers and uplift the team's design quality bar. You bring: a Bachelor's or Master's in Electronics / VLSI / Computer Engineering, 8+ years of digital design experience on ASIC / SoC projects, strong Verilog / SystemVerilog skills, hands-on with synthesis (Design Compiler / Genus), STA (PrimeTime / Tempus) and lint / CDC tools, and a deep understanding of low-power design techniques (clock gating, power gating, MV / UPF). Nice to have: experience with high-speed interfaces (PCIe, DDR, USB, Ethernet), DFT (scan, MBIST, ATPG), or RISC-V / Arm SoC work.

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